P.01
PROFESSIONAL
Broadcast Recording Automation Platform (In progress)
Next.js, Python, PostgreSQL, AWS Elemental Live, EVS Cerebrum
- Orchestrates automated game recording across AWS Elemental Live and EVS Cerebrum from a centralized request and configuration interface.
- Integrates the ESPN API to automatically detect scheduled games, create and name recording events, and generate configuration files from game metadata.
- Designed strict network isolation between internet-facing services and broadcast equipment to prevent direct external access.
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P.02
PROFESSIONAL
Control Room Scheduling Automation
Next.js, TypeScript, Turso, Vercel, Raspberry Pi 5
- Ingests When-I-Work ICS feed and ESPN game data; drives 4 Raspberry Pi DAKboard displays with live per-panel crews.
- Replaced manual schedule populating and panel routing across 60+ games per season.
- Admin dashboard allows for live schedule overrides and crew assignment changes; all changes reflected in real-time across all displays.

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P.03
PROFESSIONAL
NCAA Archive Automation
Google Apps Script, ESPN/NCAA APIs
- Automated update of Texas A&M game broadcast archive documentation in Google Sheets, filling box scores, game locations, and opponents.
- Reduced manual entries from 10,000+ to under 500 by integrating multiple public sports APIs.
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P.04
ACADEMIC
Smart Garage Parking System (Senior Capstone sponsored by FLUOR)
C++, Python, LiDAR, OpenCV, FastAPI, React
- Led development of an assisted parking system using LiDAR-based space detection, vehicle tracking, and Bezier-curve path planning to provide real-time parking guidance.
- Designed and 3D-modeled a LiDAR/Raspberry Pi housing and tripod-mounted sensing unit; implemented high-frequency LiDAR data collection with UART connectivity.
- Developed computer vision algorithms to detect and model garage walls from LiDAR point clouds and created real-time vehicle tracking using bumper point clusters.
- Integrated the system with FastAPI and React to provide a live interface for guidance feedback as the user is parking.



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P.05
ACADEMIC
8-Bit Pipelined Adder
Cadence Virtuoso
- Designed Inverter, NAND2, and XOR2 standard cells from logic schematics through transistor-level physical layouts using metal and polysilicon; verified with DRC and LVS.
- Applied a hierarchical design flow to integrate standard cells into full adders, 4-bit adders, and an 8-bit pipelined adder.
- Validated functionality and timing through hierarchical testbench simulations.

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P.06
ACADEMIC
ARMv8 Single-Cycle Processor
Verilog, Linux
- Designed and implemented a single-cycle ARMv8 processor in Verilog, integrating the control unit, ALU, register file, memory, and sign extender.
- Implemented support for the ARMv8 instructions LDUR, STUR, ADD, SUB, AND, and OR.
- Developed and debugged the processor in a Linux environment using the command line and Emacs.

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P.07
PERSONAL
Salvaged Stadium LED Panel
ESP32, Wireshark
- Reverse engineered a proprietary NovaStar Ethernet control protocol using Wireshark and analyzed communication between the controller and LED receiving hardware.
- Developed an ESP32-based interface to investigate direct control of the panel's HUB interface and characterize its communication protocol.

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P.08
PERSONAL
Gym Timer IR Controller
ESP32, C++, NEC IR protocol
- Reverse-engineered a salvaged gym timer's proprietary IR command set through systematic NEC protocol analysis and command-space testing.
- Designed and built a discrete transistor IR driver circuit and ESP32-based Wi-Fi controller for remote timer operation.

08 / 08END OF INDEX